1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more particularly, to a circuit and method for generating an output control signal in a synchronous semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices used as main memories in a computer system perform their role by inputting/outputting data to/from memory cells. The speeds of the data input/output operations of the semiconductor memory devices are important factors in determining the operating speed of the computer system. To improve the operating speed of the semiconductor memory devices, a synchronous dynamic random access memory (SDRAM, Synchronous DRAM) device in which internal circuits are controlled in synchronization with a generated clock signal from the computer system has been used.
Generally, the SDRAM uses a Column Address Strobe (CAS) latency function to increase an operation frequency. The CAS latency is defined as a time delay that is needed from the time of application of a read command before an outputted data signal can be presumed to be valid. This time delay can be represented as an integer number of cycles of a generated external clock signal with the read command being synchronized with that external clock.
Since the actual time delay (tAA) is constant for a given SDRAM, the CAS latency may be changed as a function of the operation frequency of the device. For example, if the tAA is 15 ns and the operation frequency is 200 MHz, the CAS latency becomes 3 because the period of the external clock signal is 5 ns. If the tAA is 15 ns and the operation frequency is 333 MHz, the CAS latency becomes 5 because the period of the external clock signal is 3 ns.
FIG. 1 illustrates a conventional output control signal generating circuit of a synchronous semiconductor memory device. Referring to FIG. 1, an output control signal generating circuit 100 includes a multiplexer 110 and a shift register 120.
The shift register 120 shifts a read master signal (RM) sequentially in response to an output control clock signal (PCLKDQ). PCLKD, which represents a signal generated through a delay locked-loop circuit (DLL, not shown) included in the synchronous semiconductor memory device, controls a data signal to be outputted in synchronization with the external clock signal (not shown). Typically, PCLKD is generated before the generation of the corresponding external clock signal in order to satisfy a condition where tAC (output data access time from external clock) is zero. A read master signal (RM), as a signal indicating the output interval of the data, is synchronized with an internal clock signal (not shown), which is the external clock signal delayed by a predetermined time.
The multiplexer 110 selectively outputs one of the output signals (RM_S1A, RM_S2A, RM_S3A, RM_S4A) of the shift register 120 as an output control signal (LATENCY) in response to CAS latency signals (CL2, CL3, CL4, CL5, respectively) indicating the activation of a CAS latency. The output control signal (LATENCY) is applied to an output buffer (not shown) included in the synchronous semiconductor memory device to cause the data to be outputted (i.e. activated) during an appropriate data output time interval.
FIG. 2 illustrates a timing diagram of the operation of the output control signal generating circuit shown in FIG. 1 when the CAS latency is 3. An internal clock signal (PCLK), which is generated from an external clock signal (ECLK) having a period TCC1, is delayed to time T1 from the rising edge of external clock (ECLK). An output control clock signal (PCLKDQ) is set such that it is generated earlier (T2 time) than the rising edge of a portion (ECLK1) of the external clock (ECLK).
A significant disadvantage of the circuit shown in FIG. 1 is that since the output control clock signal (PCLKDQ) typically leads the read master signal (RM), which is synchronized to the phase of the internal clock signal (PCLK), invalid read master signal (RM) may be sampled in the first cycle shown in FIG. 2 for an exemplary CAS latency of 3. To sample valid read master signal (RM), the output control clock signal (PCLKDQ) needs to be delayed by a time TD as shown in FIG. 2. The delay time (TD) and a resulting delayed output control clock signal (PCLKDQ_D) are shown in FIG. 2, and can be represented by the numerical expression,
(TCC1xe2x88x92T2)+TD greater than T1, TD greater than T1xe2x88x92(TCC1xe2x88x92T2)
Generally, in a device using the DLL, the output control clock signal (PCLKDQ) is generated to occur earlier than the corresponding external clock signal in order to satisfy the tAC=0 condition, and the early activation time of PCLKDQ is set to be constant (i.e., independent of the operating frequency.) Thus, as the frequency of the external clock signal (ECLK) increases (that is, as the period (TCC1) of ECLK decreases), the delay time (TD) needs to be increased. Thus, since the conventional synchronization circuits have no provisions for variable synchronization delays, invalid output signals from output control signal generating circuit 100 may be generated at higher clock frequencies, thereby providing invalid output data from the SDRAM.
According to a feature of an embodiment of the present invention, there are provided a circuit and a method for generating an output control signal in a synchronous semiconductor memory device that is capable of varying a delay time of an output control clock signal in response to a CAS latency, and generating the output control signal by the output control clock signal having the different delay time.
According to a feature of an embodiment of the present invention, an output control signal generating circuit in a synchronous semiconductor memory device is provided which includes a clock signal transfer circuit for transferring an output control clock signal in response to a CAS latency, wherein the clock signal transfer circuit varies a total or at least one intermediate delay time of the output control clock signal controlling a data to be outputted in synchronization with an external clock signal, a sampling circuit for shifting sequentially a read master signal to generate a plurality of output signals, each one indicating an output interval of the data in response to the output control clock signal transferred through the clock signal transfer circuit, and a selection circuit for selecting one of the plurality of output signals of the sampling circuit, and for outputting the selected output signal as an output control signal in response to the CAS latency.
According to another feature of an embodiment of the present invention, the total delay time is needed for the first clocking of the read master signal, and is also needed so that an internal clock signal synchronizing the read master signal leads the output control clock signal in phase, and the internal clock signal is generated by delaying the external clock signal to a predetermined time.
According to another feature of an embodiment of the present invention, the maximum time needed for shifting the read master signal once in the sampling circuit is less than a period of the external clock signal.
According to another feature of an embodiment of the present invention, the clock signal transfer circuit includes, a first clock signal transfer circuit for transferring the output control clock signal to the sampling circuit when a CAS latency is 2, a second clock signal transfer circuit including a first and a second delay circuits for transferring the output control clock signal delayed to the extent of the total delay time through the first and the second delay circuits and the output control clock signal delayed through the second delay circuit to the sampling circuit respectively when the CAS latency is 3, a third clock signal transfer circuit including a third, a fourth and a fifth delay circuits for transferring the output control clock signal delayed to the extent of the total delay time through the third, the fourth and the fifth delay circuits, the output control clock signal delayed through the fourth and the fifth delay circuits, and the output control clock signal delayed through the fifth delay circuit to the sampling circuit respectively when the CAS latency is 4, and a fourth clock signal transfer circuit including a sixth, a seventh, a eighth and a ninth delay circuits for transferring the output control clock signal delayed to the extent of the total delay time through the sixth, the seventh, the eighth and the ninth delay circuits, the output control clock signal delayed through the seventh, the eighth and the ninth delay circuits, the output control clock signal delayed through the eighth and the ninth delay circuits, and the output control clock signal delayed through the ninth delay circuit to the sampling circuit respectively when the CAS latency is 5, wherein each delay time of a first delay time delayed through the first and the second delay circuits, a second delay time delayed through the third, the fourth and the fifth delay circuits, and a third delay time delayed through the sixth, the seventh, the eighth and the ninth delay circuits increases in the first to the third delay times sequence.
According to a feature of an embodiment of the present invention, a method for generating an output control signal in a synchronous semiconductor memory device is provided which includes the steps of a) transferring an output control clock signal in response to a CAS latency signal, wherein a total and an intermediate delay times of the output control clock signal controlling a data to be outputted in synchronization with an external clock signal are varied, b) shifting sequentially a read master signal indicating an output interval of the data in response to the output control clock signal transferred through the a) step, and c) selecting one of shifted read master signals in the b) step, and outputting the selected read master signal as an output control signal in response to the CAS latency signal.
According to another feature of an embodiment of the present invention, the total delay time is needed for the first clocking of the read master signal, and is also needed such that an internal clock signal synchronizing the read master signal leads the output control clock signal in phase, and the internal clock signal is generated by delaying the external clock signal to a predetermined time.
According to another feature of an embodiment of the present invention, the maximum time needed for shifting the read master signal once in the b) step is less than a period of the external clock signal.
Circuit and method for generating an output control signal in a synchronous semiconductor memory device of the present invention vary a total or at least one intermediate delay time of an output control clock signal according to a CAS latency, and may prevent the malfunction of the synchronous semiconductor memory device operating in high frequency by generating an output control signal from the output control clock signal having a different delay time.
In an alternate embodiment of the present invention, an output control signal generating circuit in a synchronous semiconductor memory device preferably comprises a plurality of selectable clock signal transfer circuits, each circuit providing at least one unique time delay to an applied clock signal, and a first selection means for enabling only one clock signal transfer circuit from the plurality of clock signal transfer circuits. The output control signal generating circuit also preferably includes: a sampling circuit for sampling an applied read master signal in response to at least one signal from the enabled clock signal transfer circuit and generating a plurality of output signals, each output signal representing the applied read master signal delayed by a unique amount of time; and a second selection means for outputting only one of the plurality of output signals.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.